Serial RapidIO IP

SI-FPGA-SRIO: Overview

Sheldon Instruments offers a Serial RapidIO (SRIO) core with a highly efficient design architecture characterized by low resource utilization and low transmit and receive latencies.

The SRIO core handles all of the layer implementation details, starting with the Physical Layer, the Transport (routing) Layer, and the Logic Layers that supports multiple protocols that define the type of data exchanges between endpoint devices.

For more demanding applications, Sheldon Instruments can custom design the interface to fit your needs, or provide technical support for those designing their own interfaces.

Key Features

	32 bit wide datapath, single lane (x1) interface.
	Highly integrated into the SDRAM Memory Controller architectures.
	Seemless handling of all layer implementation details.
	Integrated DMA.

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