Multi Function I/O Module for DSP Boards


Product Details:

Overview

Technical Specifications

Ordering Information

Datasheet (pdf)


Related Information:

DSP Boards

Accessories

Library for LabVIEW

Libray for Visual Basic

Technical Support


SI-MOD68xx: Technical Specifications


Analog Inputs

Product  Analog Inputs
(16 bit Resolution)
 
Additive Sampling Rate 
SI-MOD6816-100  16 single ended or 8 differential   100khz  
SI-MOD6832-100  32 single ended or 16 differential   200khz  
SI-MOD6800-100  64 single ended or 32 differential   400khz  
SI-MOD6816-250  16 single ended or 8 differential  250khz  
SI-MOD6832-250  32 single ended or16 differential   500khz  
SI-MOD6800-250   64 single ended or 32 differential   1Mhz  

+/-10Vp maximum input voltage level, or +/-9.5Vp maximum for the "HG" option.
High input impedance minimum 1Mohm, DC coupling.
Precision differential instrumentation amplifiers with gains of 1, 2, 5, 10, part #AD8250 (Analog Devices).
4:1x2 MUX part #DG409
Each MUX-PGA-ADC group has 0hz to 100khz/250khz muxed time division sampling on 16 channels, for a maximum additive rate of 400khz/1Mhz on all channels, respectively.
Up to 4 distinct inputs are simultaneously sampled, one from each MUX-PGA-ADC group.
Successive Approximation ADCs with 16 bits of resolution:
100khz part ADS8320/25 (Burr Brown).
250khz part LTC1864 (Linear Technology).
Flexible input termination, each channel individually programmable for differential or single ended operation.
Optional High Gain (-HG) amplification, adds a second amplifier with gains of 1, 2, 5, 10, part #ADS8250 (Analog Devices), extending gain ranges from 1 to 100.

 

Timing

2 internal DDSes, 27 bit resolution phase accumulators.
4 internal programmable Event Counters, based on divide-by-n 32 bit resolution counters.
Flexible switching matrix allows timing signals to be routed from onboard resources as well external sources (Quadrature Encoders, Pulse I/Os).

Digital I/O

36 lines of general purpose digital I/Os:

4 lines programmable as general purpose I/Os, or as a pair of Quadrature Encoder inputs, or as 4 bidirectional Pulse/Frequency I/O lines.
Secondary bi-directional 32 bit port, with programmable directional control as two individual 16 bit ports.

Analog Outputs (optional)

"-8DAC" or a "-16DAC" option: Up to 8 or 16 DACs for analog output channels, part LTC2600 (Linear Technology).
Each output has 0hz to 180khz update rates.
16 bits of resolution.
+/-10Vp bipolar voltage range.
Fixed 40khz, 1-pole smoothing filter.

PC Interface

PCI initiated bus master transfer speeds through SI-DSP carrier cards:

Up to 132Mbyte/sec bursts with block sizes of eight (8) 32 bit words.
Up to 25Mbyte/sec sustained transfers of any block size, using the DSP carrier card's DMA.

General Features

On board 32KByte EEPROM contains offset/gain errors, loaded to FPGA for real time digital calibration on all analog I/O.
Xilinx XC3S500E Spartan FPGA, internal and external hardware triggers and sample clocks, software triggers.
Fully programmable with QuVIEW, an accelerator library for LabVIEW.
Fully programmable with QuBASE, an accelerator library for Visual Basic.
Full suite of development tools from Sheldon Instruments and several third parties.
Driver support for all Windows and Linux.

Physical Dimensions & Electrical Requirements

3.7"(L) x 3.7"(H), 0.18lbs or 85 grams.
Supply Voltages: 3.3V for logic circuitry (1.2V and 2.5V generated with onboard regulators), 5V for 32 bit port buffers, and +/-12V for analog circuitry.
7 Watts typical with minimum configuration: +12Vdc@0.25A, -12Vdc@0.2A, 5Vdc@0.1A, 3.3Vdc@0.35A.
14 Watts typical with maximum configuration: +12Vdc@0.55A, -12Vdc@0.5A, 5Vdc@0.1A, 3.3Vdc@0.35A.