TMS320VC33 DSP Board for PCI Bus


Product Details:

Overview

Technical Specifications

Ordering Information

Datasheet (pdf)


Related Information:

Peripheral Boards

Accessories

Software Tools

Hardware Tools

Technical Support


SI-C33DSP-PCI: Technical Specifications


Processor

Texas Instruments TMS320VC33:

150Mhz Clock Frequency.
Single DMA channel.

Memory

SRAM Options:

"-128" option: 128K x 32 bit words one (1) wait state dual access SRAM on C33's primary bus.
"-512" option: 512K x 32 bit words one (1) wait state dual access SRAM on C33's primary bus.
"-1M" option: 1M x 32 bit words one (1) wait state dual access SRAM on C33's primary bus.

 

Interface to Host

PCI initiated bus master transfer speeds:

Up to 132Mbyte/sec bursts with block sizes of eight (8) 32 bit words.
Up to 12Mbyte/sec sustained transfers of any block size, using DMA.

Three 32 bit, bi-directional communications modes between TMS320VC33 primary bus and the 9054:

Dual access mode.
Bus master mode, using the 9054 as the PCI bus mastering.
Bus master mode, using the DSP as the PCI bus mastering.

PCI Bus Bridge PCI9054:

The 9054's internal registers are mapped into the C33's primary bus, address space starting at 0xFF0000.

Interrupts:

INT0 used by C33 for basic communication and DMA transfer initialization.
INT2 and INT3 available on 120 pin expansion connector.

Peripheral Expansion

One external 100 pin half pitch DSUB connector, and two 120 pin metric socket connectors:

First 120 pin socket is designated P5, for interfacing custom daughter board to the DSP's bus.
Second 120 pin socket is designated P6, for interfacing external user defined signals to custom daughter board. Linked only to externally accessible 100 pin half pitch DSUB connector, P8.
External 100 pin, half pitch (0.050"), Series III DSUB connector, designated P8, for interfacing external user defined signals to P6. AMP part 787169-9, 787170-9, or 787362-9; Thomas & Betts part HFR100RA29CS1.

P5 120 pin metric connector decodes 8Kx32 words, mapped into the C33's primary bus, address space ranging from 0xFE0000 to 0xFE1FFF. P5 contains the following C33 signals:

Address: A[15:0].
Data: D[31:0]
Control: Control: R/W, STRB, XINT[0:1] (DSPINT[2:3]), RDY, XCLK[0:1] (DSP H[1:3]).
Host +3.3Vdc, +5Vdc, +12Vdc, -12Vdc, regulated +1.8Vdc and GND.

Miscellaneous Connectors:

One 16 pin header for DSP I/O signals: Serial port 0, XF[0:1], TMCK[0:1]
One 14 pin header for JTAG port

Software:

Win98/2000/XP and Linux driver support.
Extensive QuVIEW DSP-resident libraries for LabVIEW, including examples for real time acquisition, signal processing, and control.
Extensive QuBASE DSP-resident libraries for Visual Basic, including examples for real time acquisition, signal processing, and control.
Sample code for COFF loaders, PC <-> DSP communications source code and SI-DDK.
Compatible with separately purchased TI debuggers, C/C++ compilers, assemblers and linkers.

Physical Dimensions & Electrical Requirements:

Half size PCI-bus card measuring 6.4"(L) x 3.9"(H).
1 watt typical (2 watts maximum) with 128Kx32 words