SI-C6713DSP-PC104p: Technical Specifications
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Processor
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| Texas Instruments TMS320C6713:
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225-300Mhz clock frequency.
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16 DSP DMA channels
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2 PCI DMA channels.
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Memory
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| SDRAM program and data memory:
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Standard 3.3V, non-buffered PC133 SDRAM in SODIMM format.
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Sizes: 64MB, 128MB, 256MB and 512MB, with x16 organizations. Only half of capacity is used.
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PC133 SDRAM module clocked from E Clock running at 75Mhz, maximum delay of memory ICs mounted on module not to exceed 7.5 nsec.
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Single bank SO-DIMMs: supports *half* of memory ICs mounted on single bank modules, with all capacity only mapped on CE2 (DSP memory region starting at 0xA0000000). The DSP's CE3 region is left empty (DSP memory region starting at 0xB000000).
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Dual bank SO-DIMMs: supports *half* of memory ICs mounted on dual bank modules, with quarter of module capacity mapped on CE2 (DSP memory region starting at 0xA0000000), and the second quarter mapped on CE3 (DSP memory region starting at 0xB000000).
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Host accessible while DSP is active, with multiple communication options.
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| Boot memory:
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512kx8 SRAM.
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Configured as Dual Access memory: Accessible by host (only while DSP is inactive/reset) for downloading COFF files. Accessed by DSP during its boot loading process.
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Mapped on CE1 (DSP memory region starting at 0x90000000).
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Interface to Host
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| PCI initiated bus master transfer speeds:
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Up to 132Mbyte/sec bursts with block sizes of eight (8) 32 bit words.
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Up to 25Mbyte/sec sustained transfers of any block size, using DMA.
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| Eight 32 bit, bi-directional communications modes between TMS320C6x and the PCI9054:
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Host target/slave access mode, combined with DSP I/O or DSP's DMA engine.
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Block Mode DMA Bus Master mode, using the PCI9054 as the PCI bus master, combined with DSP I/O or DSP's DMA engine.
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PCI Initiated/Local Master with the DSP as the PCI bus master, with DSP I/O or DSP's DMA engine.
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| PCI Bus Bridge PCI9054:
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The PCI9054's internal registers are tied onto the C6x's EMIF bus, mapped on CE0 (DSP memory region starting at 0x80000000).
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| Four C6x routable interrupts:
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Up to three C6x interrupts can be routed for basic communication and DMA synchronization.
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Up to two C6x interrupts can be routed to expansion connectors.
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| PC104-ISA connector:
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Passive, optional PC104-ISA connector for stacking legacy cards.
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Peripheral Expansion
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| One external 2mm pitch, 5x30 (150 contacts) socket connector for interfacing the expansion board to the DSP's bus, or linking to all of the DSP's peripheral ports (McBSP, McASP, HPI/GPIO, Timers). The DSP Expansion connector decodes 64Kx32 words, mapped into the DSP's EMIF bus, which contains the following signals:
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Address: A[15:0] (DWord Boundary).
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Data: D[31:0].
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Control: X_R/Wn, X_CSn, X_INT[1:0] (software routable to DSP's EXTINT[7:4]), X_RDY, X_CLK[1:0].
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Peripheral Port: McBSP[1:0], HPI/GPIO, TINP[1:0], TOUT[1:0].
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Host +3.3Vdc, +5Vdc, +/-12Vdc, +1.8Vdc and GND.
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| Miscellaneous Connectors:
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One 14 pin header for JTAG port.
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Software
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Win98/2000/XP and Linux driver support.
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Extensive QuVIEW DSP-resident libraries for LabVIEW, including examples for real time acquisition, signal processing, and control.
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Extensive QuBASE DSP-resident libraries for Visual Basic, including examples for real time acquisition, control and analysis.
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Sample code for COFF loaders, PC <-> DSP communications source code and SI-DDK.
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Compatible with separately purchased TI debuggers, C/C++ compilers, assemblers and linkers.
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Physical Dimensions & Electrical Requirements
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PCI-104 card measuring 3.5"(L) x 3.775"(H).
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2.25 watts typical (4 watts maximum) with 128MB SDRAM.
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